Got rid of warnings

Need to get rid of all the warnings when running Clippy

Author: Roeegg2

kernel/Cargo.lock

@@ -8,7 +8,7 @@ limine = { version = "0.4.0", optional = true }
 
 alloc = { version = "1.0.0", package = "rustc-std-workspace-alloc"}
 
-modular-bitfield = { version = "0.11.2"}
+modular-bitfield = { version = "0.12"}
 utils = { path = "../utils" }
 macros = { path = "../macros" }
 

kernel/Cargo.toml

@@ -4,7 +4,7 @@ use core::{ptr::from_ref, slice::from_raw_parts};
 
 use utils::sanity_assert;
 
-use crate::dev::bus::pcie::{self, PcieManager};
+use crate::dev::bus::pcie;
 
 use super::{AcpiError, AcpiTable, SdtHeader};
 

kernel/src/acpi/mcfg.rs

@@ -19,7 +19,7 @@ pub enum IoApicError {
     /// The GSI passed in is invalid
     InvalidGsi,
     /// IDT Error
-    IdtError(()),
+    IdtError,
 }
 
 /// An IRQ override mapping
@@ -61,7 +61,7 @@ struct IoApicReg;
 
 /// The IO APIC's redirection table entry, which configure the behaviour and mapping of the
 /// external interrupts
-#[bitfield]
+#[bitfield(bits = 64)]
 #[derive(Debug, Clone, Copy)]
 #[repr(u64)]
 struct RedirectionEntry {
@@ -150,7 +150,7 @@ impl IoApic {
         // TODO: Return error if the offset is invalid
         unsafe {
             self.io_sel.write(offset);
-            let mut raw: u64 = self.io_win.read() as u64;
+            let mut raw: u64 = self.io_win.read().into();
             self.io_sel.write(offset + IoApicReg::red_tbl_to_index(1));
             raw |= (self.io_win.read() as u64) << 32;
 

kernel/src/arch/x86_64/apic/ioapic.rs

@@ -112,7 +112,7 @@ pub enum DeliveryStatus {
 }
 
 /// Represents the LVT register
-#[bitfield]
+#[bitfield(bits = 32)]
 #[derive(Debug, Clone, Copy)]
 #[repr(u32)]
 pub struct LvtReg {
@@ -161,7 +161,7 @@ impl LocalApic {
         );
     }
 
-    /// Enables the local APIC in the IA32_APIC_BASE MSR, in case firmware didn't do it already
+    /// Enables the local APIC in the `IA32_APIC_BASE` MSR, in case firmware didn't do it already
     #[inline]
     fn hardware_enable() {
         const APIC_ENABLE: u32 = 1 << 11;
@@ -185,7 +185,7 @@ impl LocalApic {
 
         // Initialize the local APIC
         unsafe {
-            // Make sure the APIC enable bit on the IA32_APIC_BASE MSR is set
+            // Make sure the APIC enable bit on the `IA32_APIC_BASE` MSR is set
             Self::hardware_enable();
 
             // Configure the SIV and software enable the APIC
@@ -416,7 +416,7 @@ pub unsafe fn add(base: PhysAddr, acpi_processor_id: u32, apic_id: u32, flags: u
     )));
 }
 
-/// Marks the matching processor's LINT as NMI with the passed flags, making the other ExtInt
+/// Marks the matching processor's LINT as NMI with the passed flags, making the other `ExtInt`
 ///
 /// SAFTEY:
 pub unsafe fn config_lints(acpi_processor_id: u32, lint: u8, flags: u16) {

kernel/src/arch/x86_64/apic/lapic.rs

@@ -19,7 +19,7 @@ pub trait Register {
 }
 
 #[derive(Clone, Copy)]
-#[bitfield]
+#[bitfield(bits = 64)]
 #[repr(u64)]
 pub struct Rflags {
     /// Carry flag
@@ -70,7 +70,7 @@ pub struct Rflags {
 
 /// The CR0 register
 #[derive(Clone, Copy)]
-#[bitfield]
+#[bitfield(bits = 64)]
 #[repr(u64)]
 pub struct Cr0 {
     /// Protection enable
@@ -111,7 +111,7 @@ pub struct Cr0 {
 pub struct Cr2(pub u64);
 
 /// The CR3 register
-#[bitfield]
+#[bitfield(bits = 64)]
 #[repr(u64)]
 pub struct Cr3 {
     /// Reserved (must be 0)
@@ -127,7 +127,7 @@ pub struct Cr3 {
 }
 
 /// The CR4 register
-#[bitfield]
+#[bitfield(bits = 64)]
 #[repr(u64)]
 pub struct Cr4 {
     /// Virtual 8086 mode extensions
@@ -208,7 +208,7 @@ pub struct Dr3(VirtAddr);
 
 /// Debug register 6 on AMD CPUs
 #[derive(Clone, Copy)]
-#[bitfield]
+#[bitfield(bits = 64)]
 #[repr(u64)]
 pub struct AmdDr6 {
     /// Debug register 0 condition
@@ -239,7 +239,7 @@ pub struct AmdDr6 {
 
 /// Debug register 7 on AMD CPUs, 64 bit
 #[derive(Clone, Copy)]
-#[bitfield]
+#[bitfield(bits = 64)]
 #[repr(u64)]
 pub struct AmdDr7 {
     /// Local breakpoint 0 enable
@@ -568,6 +568,12 @@ impl Register for Cr4 {
     }
 }
 
+impl Default for Cr3 {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
 // impl Into<u64> for MsrData {
 //     fn into(self) -> u64 {
 //         ((self.high as u64) << 32) | (self.low as u64)

kernel/src/arch/x86_64/cpu/mod.rs

@@ -52,6 +52,7 @@ pub struct VmCr;
 pub struct VmHsavePa;
 
 // TODO: Fix this
+#[allow(dead_code)]
 impl Efer {
     /// System call extension enable
     pub const SCE: u64 = 1 << 0;

kernel/src/arch/x86_64/cpu/msr.rs

@@ -19,7 +19,7 @@ pub struct FullSegmentSelector {
 }
 
 /// A segment descriptor.
-#[bitfield]
+#[bitfield(bits = 64)]
 #[derive(Debug, Clone, Copy)]
 #[repr(u64)]
 pub struct SegmentDescriptor {
@@ -41,7 +41,7 @@ pub struct Gdt {
 }
 
 /// The basic, visible part of a segment selector.
-#[bitfield]
+#[bitfield(bits = 16)]
 #[derive(Debug, Clone, Copy, Default)]
 #[repr(u16)]
 pub struct SegmentSelector {
@@ -130,24 +130,30 @@ impl SegmentDescriptor {
     const ACCESS_DPL_1: u8 = 0b01 << 5;
     const ACCESS_P: u8 = 1 << 7; // present
 
-    const _FLAGS_RESERVED: u8 = 1 << (4 + 0);
+    const _FLAGS_RESERVED: u8 = 1 << 4;
     const FLAGS_G: u8 = 1 << (4 + 1); // granuality
     const FLAGS_DB: u8 = 1 << (4 + 2); // size. 0-> 16 bit protected mode 1-> 32 bit protected
     const FLAGS_L: u8 = 1 << (4 + 3); // segment is 64 long mode. when set, DB shouldn't be
 
     #[inline]
-    fn get_base(&self) -> u32 {
+    fn get_base(self) -> u32 {
         (u32::from(self.base_1()) << 24) | u32::from(self.base_0())
     }
 
     // TODO: Make this function const
     /// NOTE: The size of the limit is actually 20 bits, not 32
     #[inline]
-    fn get_limit(&self) -> u32 {
+    fn get_limit(self) -> u32 {
         (u32::from(self.limit_1()) << 16) | u32::from(self.limit_0())
     }
 }
 
+impl Default for SegmentDescriptor {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
 impl Register for Cs {
     #[inline]
     unsafe fn read() -> Self {

kernel/src/arch/x86_64/gdt.rs

@@ -32,7 +32,7 @@ pub struct Idt([GateDescriptor; IDT_ENTRIES_NUM]);
 /// NOTE: That's not the actual ISR, that's only stub.
 pub type IsrStub = unsafe extern "C" fn();
 
-#[bitfield]
+#[bitfield(bits = 128)]
 #[derive(Debug, Clone, Copy)]
 #[repr(u128)]
 /// A gate descriptor instance. These are the entries of the IDT
@@ -181,7 +181,7 @@ impl Idt {
             asm! (
                 "lidt [{}]",
                 in(reg) &idtr,
-            )
+            );
         }
 
         log_info!("Loaded IDT successfully");
@@ -213,7 +213,7 @@ pub unsafe fn install_isr(
     gate_type: GateType,
     dpl: Dpl,
     present: Present,
-) -> Result<u8, ()> {
+) -> u8 {
     let mut idt = IDT.lock();
 
     let (entry_number, entry) = idt
@@ -232,7 +232,7 @@ pub unsafe fn install_isr(
         present,
     );
 
-    Ok(entry_number as u8)
+    entry_number as u8
 }
 
 unsafe extern "C" {

kernel/src/arch/x86_64/interrupts.rs

@@ -20,7 +20,7 @@ pub mod paging;
 pub static CPU_VENDOR: FastLazyStatic<CpuVendor> = FastLazyStatic::new(CpuVendor::Invalid);
 
 #[derive(Debug, Clone, Copy, PartialEq)]
-/// The x86_64 CPU vendors Funderberker supports
+/// The `x86_64` CPU vendors Funderberker supports
 pub enum CpuVendor {
     /// We're running on an AMD CPU
     Amd,